Direct Memory Access (DMA)

Introduction

We haven't talked a lot about I/O devices. Our simple model of the computer is a CPU, memory, and a bus to connect the two.

The assumption about I/O devices is that it's really, really slow, compared to the speed of the CPU. I/O devices include keyboard, mouse, printers, etc. While some devices may need quick response, usually when downloading or uploading data, I/O devices are generall considered slow.

Rather than the CPU "polling" or asking the I/O device if it needs some action taken on its behalf, the I/O device interrupts the CPU by sending an interrupt signal (such as a positive edge). The CPU then temporarily stops what it is doing, and services the I/O device.

The code to do this is called the interrupt handler. The handler must already be loaded in memory before the interrupt has occurred (often it's already there when the machine boots up).

Occasionally, an I/O device needs to read from memory or write to memory. This can be very slow, as we shall see.

Diagram of I/O devices

The following is a modified diagram of the basic computer. It now includes an I/O device.

Now imagine that the I/O device wants to store a lot of data to memory. Perhaps you have just taken some pictures on a digital video camera, and want to store this information.

One way to do this is to alert the CPU that the I/O device wants to store data to memory. These are the steps that might be taken.

CPU sends signal to I/O device to put data on data bus.
I/O device places data on data bus, and signals it has done so.
CPU reads in the data into a register, and signals the I/O device that it has finished reading the data.
CPU signals memory that it is ready to write data to memory.
CPU places address and data on data bus.
Memory writes data from data to some memory location.
Memory signals CPU it has written data.

Thus the data flows from the I/O device to the CPU, and from the CPU to memory.

DMA

It should seem obvious that there is a quicker way to put the data in memory. After all, these are lecture notes on "Direct Memory Access", so the idea is to access memory directly, and avoid the CPU as the middle man.

After all, how can memory who is sending signals to it? How does it know that the CPU sends signals, instead of the device itself.

If the I/O device generates all the signals that the CPU does, then the I/O device can bypass the step where the data transfers to the CPU, thus, potentially doubling the speed.

Problems

There are some potential problems. Before we introduced I/O devices, the CPU was in charge of the bus. It was in control of when the bus was being accessed.

With I/O devices, both the CPU and the I/O device may be contending to use the address and data bus, so there needs to be some way of arbitrarting (deciding) who gets the bus at which time.

Furthermore, if there are more than one I/O devices trying to access the bus, we may have to decide which I/O device gets control.

One potential solution to the problem is to have a hardware device that is a bus arbitrator, which decides which device gets the bus, and helps coordinate who sends what signals to the memory.

Summary

DMA (Direct Memory Access) is a way for I/O devices to bypass the CPU when accessing memory. This is done by sending the same signals to memory that the CPU would send.

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